This application claims the priority benefit of Taiwan application serial no. 90127831, filed Nov. 9, 2001.
1. Field of the Invention
This invention relates in general to a circuit and a method for measuring a capacitance, and more particularly relates to a circuit and a method for measuring a capacitance based upon charges.
2. Description of Related Art
Unavoidably, there are capacitors or capacitive loads formed in an integrated circuit (IC). For understanding effects from the capacitors or capacitive loads, it has to precisely measure the capacitances of the capacitors or capacitive loads. FIGS. 1Axcx9c1C shows a conventional circuit diagram and its corresponding bias conditions for measuring a capacitance of a capacitor. As shown in FIG. 1A, the circuit configuration comprises four MOS (Metal oxide Semiconductor) transistors P1, P2, N1 and N2, in which the sources of the PMOS transistors P1 and P2 are coupled to a power source VDD, and the sources of the NMOS transistors N1 and N2 are coupled to a power source GND. By measuring a current flowing through the capacitor C, its capacitance can be determined thereby. The measuring scheme using the above circuit is discussed in brief as follows.
Referring to FIG. 1A, non-synchronized voltages Vp, Vn are respectively applied to the gates of the PMOS transistor P1 and the NMOS transistor N1, and a voltage of VDD is applied to both of the gates of the PMOS transistor P2 and the NMOS transistor N2. Accordingly, a current flows from the PMOS transistor P1 to the capacitor C to charge the capacitor (current IC1). Then, the capacitor C is discharged using a current I through the NMOS transistor N1 to the ground.
Referring to FIG. 1B, the non-synchronized voltages Vp, Vn are respectively applied to the gates of the PMOS transistor P2 and the NMOS transistor N2, and the voltage of VDD is applied to both of the gates of the PMOS transistor P1 and the NMOS transistor N1. Accordingly, a current flows from the PMOS transistor P2 to the capacitor C to charge the capacitor (current IC2). Then, the capacitor C is discharged using a current I through the NMOS transistor N2 to the ground.
Next, referring to FIG. 1C, the non-synchronized voltages Vp, Vn are respectively applied to the gates of the PMOS transistor P1, P2 and the NMOS transistor N1, N2. Then, currents I flow through the NMOS transistors N1, N2 to the ground without flowing through the capacitor C.
A current flowing through the capacitor C can be calculated by adding the currents measured from FIGS. 1A, 1B and then subtracting the current measured from FIG. 1C, there by the capacitance of the capacitor C can be obtained. However, there are some drawbacks using the circuit above to measure the capacitance. It requires three steps to measure the current through the capacitor, which is complicated and not accurate.
According to the foregoing description, it is an object of this invention to provide a circuit for measuring a capacitance and a capacitance measuring method based upon the circuit, thereby the capacitance can be fast and accurately measured.
It is another object of this invention to provide a circuit for measuring a capacitance for reducing the pad number of the circuit and therefore simplifying its fabricating process.
According to the objects mentioned above, the invention provides a circuit for measuring a capacitance of a capacitive load. The circuit comprises elements as follows. A first type-1 MOS transistor (for example a PMOS transistor) has a source coupled to a first power source (for example VDD). A second type-1 MOS transistor has a source coupled to a second power source, and a first input voltage that is applied to the gates of the first and the second type-1 MOS transistor. A first type-2 MOS transistor (for example a NMOS transistor) has a source coupled to a third power source having a level lower than the first power source (for example a ground level), and the drain of the first type-2 MOS transistor is coupled to the drain of the first type-1 MOS transistor. A second type-2 MOS transistor has a source coupled to the third power source, and the drain of the second type-2 MOS transistor is coupled to the drain of the second type-1 MOS transistor, and a second input voltage is applied to the gates of the first and the second type-2 MOS transistor, wherein the first and the second input voltages are non-synchronized. A capacitive load is coupled between the drains of the first and the second type-1 MOS transistors. And a pad is coupled to the drain of the second type-1 MOS transistor, wherein the third power source is applied to the pad such that the voltage at the two ends of the capacitive load are the same for measuring a first output current, and the pad is floated such that the voltage at the two ends of the capacitive load are different for measuring a second output current, and then a current flowing through the capacitive load is obtained by subtracting the first and the second output current. Thus, the capacitance of the capacitive load is calculated.
The invention further provides a circuit for measuring a capacitance of a capacitive load. The circuit comprises elements as follows. A first type-1 MOS transistor (for example a PMOS transistor) has a source coupled to a first power source (for example VDD). A second type-1 MOS transistor has a source coupled to a second power source, and a first input voltage is applied to the gates of the first and the second type-1 MOS transistor. A first type-2 MOS transistor (for example a NMOS transistor) has a source coupled to a third power source having a level lower than the first power source (for example a ground level), and the drain of the first type-2 MOS transistor is coupled to the drain of the first type-1 MOS transistor. A second type-2 MOS transistor has a source coupled to the third power source, and the drain of the second type-2 MOS transistor is coupled to the drain of the second type-1 MOS transistor, and a second input voltage is applied to the gates of the first and the second type-2 MOS transistor, wherein the first and the second input voltages are non-synchronized. A capacitive load is coupled between the drains of the first and the second type-1 MOS transistors. And a MOS transistor is coupled to the drain of the second type-1 MOS transistor, wherein the MOS transistor is turned on such that the voltage at the two ends of the capacitive load are the same for measuring a first output current, and the MOS transistor is turned off such that the voltage at the two ends of the capacitive load are different for measuring a second output current, and then a current flowing through the capacitive load is obtained by subtracting the first and the second output current. Thus, the capacitance of the capacitive load is calculated.
The invention further provides a method for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, a power source is applied to sources of the first and the second PMOS transistors, and a ground is applied to sources of the first and the second NMOS transistors. A first input voltage is applied to gates of the first and the second PMOS transistors and a second input voltage is applied to gates of the first and the second NMOS transistors simultaneously, wherein the first and the second input voltages are non-synchronized.
Then, the ground is applied to the pad such that the voltage at the two ends of the capacitive load are the same for measuring a first output current, and the pad is floating such that the voltage at the two ends of the capacitive load are different for measuring a second output current. By subtracting the first and the second output currents, a capacitor current flowing through the capacitive load is obtained. Thus, the capacitance of the capacitive load is calculated using the capacitor current.
By means of the circuit configuration above, the non-synchronized voltage is applied to both of the gates of the PMOS transistors P1, P2 and NMOS transistors N1, N2 as the circuit of the invention is activated. Therefore, the measurement of the capacitance can be faster and more accurate. Furthermore, for measuring the capacitance, it requires only two steps and therefore, the measuring steps can be reduced and simplified. Moreover, the pad number for the circuit is reduced and accordingly the manufacturing process for the circuit of the invention can be simplified.